One of several challenges facing memory chip designers is to develop memory chips that minimize power consumption. As such, energy efficiency has become an important item for optimization in memory chips. Mobile devices need memory chips that are capable of extending battery life by not consuming as much power and desktop systems need to reduce power to meet noise or power consumption limitations. Memory chips are consuming an increasing amount of the allowable power allocation in computing devices and thus, efforts are being made to reduce power consumption and increase energy efficiency.
Memory chip manufacturers are attempting to meet this demand for energy efficient memory chips by manufacturing memory chips capable of operating in multiple power modes such as active, standby, power-down and deep-power-down. In order to process a memory request, the memory chip must be in active mode. Traditionally, the remaining modes are in the order of decreasing power consumption. As such, standby mode consumes more power than power-down mode and deep-power-down mode consumes the least amount of power. Each of these power modes also requires an increased amount of time to transition back to active mode. Therefore, it takes less time for a memory chip to return to active mode from standby mode than it does for a memory chip to return to active mode from power-down mode.
Placing memory chips in lower power states when they are not in use by the computing device system using the memory chip can increase energy efficiency. In prior art systems, the challenge for system designers has been to use these modes effectively to reduce power consumption. As such, external memory controllers must be programmed to set the memory chips in low power modes when not in use. This requires designers to spend a considerable amount of time and effort developing code and designs that are capable of accurately knowing when to place the memory chips into the various low power modes.
A memory chip that can change power modes without the assistance of an external memory controller is disclosed in U.S. application Ser. No. 10/252,153, entitled Automatic Low-Power State Entry to the same named inventor, and is hereby incorporated by reference in its entirety. In this case, the memory controller must be informed that such a change took place in the memory chip. This is especially true for applications with a point-to-point connection where only one memory controller and one memory chip are involved. As such, a need exists for a memory chip that is capable of informing a memory controller of entry into a low power mode.